Computer Architecture

Spring 2021, USTC

时间地点

课程号：011135.02

3C203: 1(3,4) 5(3,4)

课程主讲

周学海教授（xhzhou@ustc.edu.cn）

主页网址：http://staff.ustc.edu.cn/~xhzhou/CA-Spring2021/CA.html

课程助教

吴豫章:752865034

高银康:592424512

李浩然:353940072

庞继泽:3022988515

钱佳明:1830010557

联系方式

地址：高能效智能计算实验室（西区活动中心北一层）

群号：341093440

考核方式

- 平时作业 10％

– 实验 40％

– 随堂测验 15%

– 期终考试 35%

考试信息

时间：

地点：

Welcome to the Spring 2021 Computer Architecture web page. The course is intended to provide a foundation for students interested in performance programming, compilers, and operating systems, as well as computer architecture and engineering. Our goal is for you to better understand how software interacts with hardware, and to understand how trends in technology, applications, and economics drive continuing changes in the field. The course will cover the different forms of parallelism found in applications (instruction-level, data-level, thread-level, request-level) and how these can be exploited with various architectural features. We will cover pipelining, superscalar, speculative and out-of-order execution, vector machines, VLIW machines, multithreading, graphics processing units, and parallel microprocessors. We will also explore the design of memory systems including caches, virtual memory, and DRAM.

Course Calendar

Week	Lecture Topic	Readings 5th Edition	Readings 6th Edition
1	1-1 体系结构简介	Ch. 1	Ch. 1
1	1-2 发展历史、现状及趋势	Ch. 1	Ch. 1
2	1-3 定量分析基础	Ch. 1	Ch. 1
2	2-1 ISA的基本概念	Appendix A	Appendix A
3	2-2 ISA的功能设计	Appendix A	Appendix A
3	2-3 ISA的实现	Appendix A	Appendix A
4	3-1 基本流水线、性能评估	Appendix C	Appendix C
4	3-2 基本流水线的扩展	Appendix C	Appendix C
5	4-1 Cache的基本概念	Appendix B.1-B.2, Ch.2.1	Appendix B.1-B.2, Ch.2.1
5	4-2 Cache的优化方法I	Appendix B.3, Ch.2.2	Appendix B.3, Ch.2.2
6	4-3 Cache的优化技术II	Appendix B, Ch.2.2	Appendix B, Ch.2.2
6	4-4-1 Cache的优化方法III 4-4-2 存储技术及优化	Appendix B.3, Ch.2.2-2.3	Appendix B.3, Ch.2.2-2.3
7	4-5 虚拟存储（2学时）	Appendix B.4, Ch.2.4	Appendix B.4 ,Ch.2.4
7	5-1 ILP的基本概念及静态指令流调度	Ch.3.1-3.2	Ch.3.1-3.2
8	5-2 动态指令流调度 I	Ch.3.4-3.5	Ch.3.4-3.5
8	5-2 动态指令流调度 II	Ch.3.4-3.5	Ch.3.4-3.5
9	5-4 分支预测	Ch.3.3, 3.9-3.10	Ch.3.3, 3.9-3.10
9	5-5 推断执行	Ch.3.6, 3.9	Ch.3.6, 3.9
10	5-6 存储器访问冲突、多发射	Ch.3.7-3.8	Ch.3.7-3.8
10	5-7 多线程技术	Ch.3.12	Ch.3.12
11	6-1 向量处理机模型 I	Ch.4.1-4.3(Appendix G)	Ch.4.1-4.3(Appendix G)
11
12	实验及习题
12	6-2 向量处理机模型 II	Ch.4.1-4.3(Appendix G)	Ch.4.1-4.3(Appendix G)
13	6-3 GPU-I	Ch. 4.4-4.9	Ch. 4.4-4.9
13	6-4 GPU-II	Ch. 4.4-4.9	Ch. 4.4-4.9
14	7-1 存储一致性 I	Ch. 5.1-5.4	Ch. 5.1-5.4
14	7-2 存储一致性 II	Ch. 5.1-5.4	Ch. 5.1-5.4
15	7-3 存储一致性 III	Ch. 5.1-5.4	Ch. 5.1-5.4
15	7-4 存储同一性	Ch. 5.1 && 5.5-5.6	Ch. 5.1 && 5.5-5.6